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APPLICATION NOTE
SH7262/SH7264 Group
High-speed Read/Write Serial Flash Memory Using the Renesas Serial Peripheral Interface
Summary
This application note describes how to read or write serial flash memory in high-speed using the SH7262/SH7264 Microcomputers (MCUs) Renesas Serial Peripheral Interface (RSPI).
Target Device
SH7262/SH7264 MCU (In this document, SH7262/SH7264 are described as "SH7264").
Contents
1. 2. 3. 4. Introduction........................................................................................................................................ 2 Applications ....................................................................................................................................... 3 Sample Program Listing.................................................................................................................. 19 References ...................................................................................................................................... 43
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1. 1.1
Introduction Specifications
* Use the serial flash memory of 2 MB (64 KB x 32 sectors, 256 bytes per page) to connect with the SH7264 MCU. * Use channel 0 of the RSPI to access serial flash memory. * Procedures are optimized to access the large volume data in high-speed.
1.2
Modules Used
* Renesas Serial Peripheral Interface (RSPI) * General-purpose I/O ports
1.3
Applicable Conditions
SH7262/SH7264 Internal clock: 144 MHz Bus clock: 72 MHz Peripheral clock: 36 MHz Renesas Technology Corp. High-performance Embedded Workshop Ver.4.04.01 Renesas Technology SuperH RISC engine Family C/C++ compiler package Ver.9.02 Release 00 Default setting in the High-performance Embedded Workshop (-cpu=sh2afpu -fpu=single -object="$(CONFIGDIR)\$(FILELEAF).obj" -debug gbr=auto -chgincpath -errorpath -global_volatile=0 -opt_range=all infinite_loop=0 -del_vacant_loop=0 -struct_alloc=1 -nologo)
MCU Operating Frequency
Integrated Development Environment C compiler Compiler options
1.4
Related Application Note
Refer to the related application notes as follows: * SH7262/SH7264 Group Example of Initialization * SH7262/SH7264 Group Interfacing Serial Flash Memory Using the Renesas Serial Peripheral Interface * SH7262/SH7264 Group Boot from the Serial Flash Memory
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2.
Applications
Connect the SH7264 MCU (Master) with the SPI-compatible serial flash memory (Slave) for read/write access using the Renesas Serial Peripheral Interface (RSPI). This application accesses serial flash memory in high-speed for large volume data. This chapter describes the pin connection example and flow charts of the sample program.
2.1
RSPI Operation
SH7264 RSPI supports full-duplex, synchronous, serial communications with peripheral devices in SPI operation using the MOSI (Master Out Slave In), MISO (Master In Slave Out), SSL (Slave Select), and RSPCK (SPI Clock) pins. The RSPI has the following features to support SPI-compliant devices: * Master/slave modes * Serial transfer clock with programmable polarity and phase (change SPI modes) * Transfer bit length selectable (8-bit, 16-bit, and 32-bit) The RSPI has two channels, channel 0 and channel 1; this application uses channel 0.
2.2
Serial Flash Memory Pin Connection
The following table lists the specifications of the SPI-compliant serial flash memory (AT26DF161A, ATMEL) used in this application.
Table 1 Serial Flash Memory Specifications Item SPI modes Clock frequency Capacity Sector size Page size Erase architecture Programming options Protect feature Description Supports SPI modes 0 and 3 70 MHz (at maximum) 2 MB 64 KB 256 bytes Chip Erase, 64 KB, 32 KB, 4 KB Byte/Page Program (1 to 256 bytes), Sequential Program In sectors
Figure 1 shows an example of serial flash memory circuit. Set the SH7264 pin functions as shown in Table 2.
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3.3 V
SH7264
RSPCK0
3.3 V
Serial flash memory AT26DF161A 2 MB
SCK (Serial Clock)
SSL00
3.3 V
CS# (Chip Select)
MOSI0
3.3 V
SI (Serial Data Input)
MISO0 3.3 V
3.3 V
SO (Serial Data Output) HOLD#
WP# (Write Protect) DIP switches
Figure 1 Serial Flash Memory Circuit Note: Pull-up or pull-down the control signal pins by the external resistor To pull up or pull down the control signal pins, determine the signal line level not to cause the external device malfunction when the MCU pin status is in high-impedance. SSL00 pin is pulled up by the external resistor to Highlevel. Pull up or down the RSPCK0 and MOSI0 pins. As the MISO0 pin is an input pin, pull up or down it to avoid floating to the midpoint voltage. Table 2 Multiplexed Pins Peripheral Pin Functions Name RSPI MISO0 MOSI0 SSL00 RSPCK0 SH7264 Port Control Register SH7264 Register Multiplexed Pin Name MD bit Setting Name PFCR3 PF12MD[2:0] = B'011 PF12/BS#/MISO0/TIOC3D/SPDIF_OUT PFCR2 PF11MD[2:0] = B'011 PF11/A25/SSIDATA3/MOSI0/TIOC3C/SPDIF_IN PFCR2 PF10MD[2:0] = B'011 PF10/A24/SSIWS3/SSL00/TIOC3B/FCE# PFCR2 PF9MD[2:0] = B'011 PF9/A23/SSISCK3/RSPCK0/TIOC3A/FRB
Note: SH7264 Multiplexed Pins MISO0, MOSI0, SSL00, and RSPCK0 pins are multiplexed, and set to general-purpose I/O ports as default. Before accessing serial flash memory, use the general-purpose I/O port control register to set the multiplexed pins to RSPI pins.
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2.3
Interface Timing Example When Accessing in High-speed
This section describes an example of the interface timing when accessing serial flash memory in high-speed. The interface timing by the typical procedure to control the SPI is explained, as well as the procedure to read/write serial flash memory in high-speed.
2.3.1
Interface Timing by the Typical Procedure to Control SPI
Figure 2 shows an example of the data transfer timing by the typical procedure to control SPI. According to the specifications of the serial flash memory used in this application, both master and slave output data on the falling edge of the clock, and latch data on the rising edge of the clock after a half cycle later. This procedure supports full-duplex communication. For details on this procedure, refer to the application note "SH7262/SH7264 Group Interfacing Serial Flash Memory Using the Renesas Serial Peripheral Interface".
tCSLS tLEAD SSL00 fSCK tSPcyc RSPCK0 tOD tDS MOSI0 bit 0 bit 1 tV tsu MISO0 txxx : Timing conditions for serial flash memory : Timing for latching data tH tOH bit 7 tDH tOH tCSLH tLAG tCSH tTD
Figure 2 Data Transfer Timing Example by the Typical Procedure to Control SPI (CPOL = 1, CPHA =1)
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2.3.2
Extending the Setup Time and the Access Width
This section describes RSPI setting and the interface timing when accessing serial flash memory in high-speed. This example extends the setup time to one cycle, to specify the RSPCK as 36 MHz, and extends the access width to the data register (SPDR) on data transfer to the longword-wide (32-bit). As this procedure requires a complex control, however, it allows the SPI to transfer data efficiently.
(1)
Extending the Setup Time
The setup time by the typical control procedure described in 2.3.1 is less than half a cycle of the RSPCK. The SH7264 data input setup time (tSU) is 15 ns at minimum. When setting the RSPCK frequency at 36 MHz at maximum (when the bus clock is 72 MHz), the half cycle is approximately 13 ns at minimum. As it does not satisfy the timing condition, extend the setup time to allow the RSPCK frequency at 36 MHz. Following example describes how to extend the setup time when using the Read Array command. The figure below shows the command sequence for the Read Array command (Opcode: H'0B). The former part of the transfer is MOSI, the SH7264 (Master) outputs commands and addresses. The latter part of the transfer is MISO, the serial flash memory (Master) outputs data. To extend the setup time, change CPOL and CPHA bits settings in the SPCMD register in the former part and latter part of the transfer. Table 3 describes the CPOL bit and the CPHA bit.
MOSI transfer (Refer to Figure 4)
SSL00 MOSI0 MISO0 H'0B addr1 addr2 addr3 dummy
MISO transfer (Refer to Figures 5 and 6)
data1
data2
data2
data n-1
data n
Figure 3 Command Sequence When Extending the Setup Time (Read Array Command)
Table 3 CPOL Bit and CPHA bit Register Name Bit 1 Command register (SPCMD) Bit Name CPOL R/W R/W Description RSPCK Polarity Setting Specifies the RSPCK polarity in master or slave mode. When transferring/receiving data between the RSPI and the other module, set the polarity of the RSPCK at the same level. 0: RSPCK = 0 when idle 1: RSPCK = 1 when idle RSPCK Phase Setting Specifies the RSPCK phase in master or slave mode. When transferring/receiving data between the RSPI and the other module, set the phase of the RSPCK at the same level. 0: Latches the data on odd edge, and outputs data on even edge 1: Outputs data on odd edge, and latches on even edge
0
CPHA
R/W
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This section describes the MOSI transfer. To extend the setup time, set the timing between the master output and slave input (latch data) as one cycle of the RSPCK. As the serial flash memory used in this application latches data on the rising edge, the SH7264 must outputs data on the preceding rising edge. There are two combinations of options for bit setting as (CPOL = 1, CPHA =0) or (CPOL = 0, CPHA = 1) for the master to output data on the rising edge. This example uses (CPOL = 1, CPHA = 0) for the following reason. When setting the CPHA bit to 1, the master (SH7264) outputs the first data bit on the first RSPCK edge (on the rising edge when the CPOL bit is 0), not upon asserting SSL signal. And the slave (serial flash memory) latches data on the first rising edge. Therefore, when setting the CPOL bit to 0, and the CPHA bit to 1, the slave latches data when the master outputs the first bit of data. This setting does not satisfy the setup condition. When using the setting (CPOL =1, CPHA = 0), the master outputs the first data bit upon asserting SSL signal. There is more than one cycle before the first rising edge of the RSPCK, the timing when the slave latches data. This setting satisfies the setup condition. From the second data bit, the master outputs data on the rising edge of the RSPCK, and the slave latches data on the next rising edge to satisfy the timing condition. The following figure shows the MOSI transfer timing when setting (CPOL = 1, CPHA = 0).
Set the RSPI as (CPOL = 1, CPHA = 0) - Specify the RSPCK as 1 when idle - Output data on the even edge - Output the first data bit upon asserting SSL
RSPCK frequency SSL00
1
2
RSPCK0 Set the RSPI as CPHA = 0 to output data upon asserting SSL. MOSI0 Master outputs the first data bit Master outputs the second data bit
Serial flash memory latches data on rising edge.
The master must output data on rising edge of the RSPCK to ensure one cycle before the timing when the slave latches data. ->Use the setting (CPOL = 1, CPHA = 0) or (CPOL = 0, CPHA = 1).
Figure 4 Interface Timing on MOSI Transfer
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This section describes the MISO transfer. As the master latches data in the MISO transfer, set CPOL and CPHA bits so that the master latches data one cycle after the slave outputs data. As the serial flash memory used in this application outputs data on the falling edge, the SH7264 must latches data on the preceding edge (falling edge). (CPOL =1, CPHA = 0) setting is already used in the MOSI transfer, however, change the setting to (CPOL 0, CPHA = 1) for the following reason. Figure 5 shows the timing without changing the settings of CPOL and CPHA bits. As the master latches data when the slave outputs data on the falling edge of the RSPCK falling edge, this setting does not satisfy the timing condition. Figure 6 shows the timing for (CPOL = 0, CPHA = 1). As the RSPCK falls when changing the RSPI setting, the slave outputs data at the same timing. Then, the master latches data one cycle after the falling edge of the RSPCK. This setting satisfies the timing condition.
RSPCK frequency SSL00
1
2
Serial flash memory outputs data on falling edge, just after commands are input.
RSPCK0
MOSI0 the last data bit
Slave outputs the first data bit Slave outputs the second data bit
Master outputs
MISO0
The timing when the master latches the first data bit
Figure 5 Interface Timing on MISO Transfer (CPOL and CPHA bits are not changed)
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Set the RSPI as (CPOL=0, CPHA=1) - Set the RSPCK as 0 when idle - Latch data on even edge RSPCK frequency SSL00 CPOL = 0 setting changes the RSPCK polarity. The timing when the master latches the first data bit 1 2
RSPCK0
Master outputs MOSI0 the last data bit
MISO0
Slave outputs the first data bit
Slave outputs the second data bit
Serial flash memory outputs data on the falling edge, just after commands are input
The master must latch data on the falling edge of the RSPCK to ensure one cycle after the timing when the slave outputs data. -> Use the setting (CPOL=1, CPHA = 0) or (CPOL = 0, CPHA = 1).
Figure 6 Interface Timing on MISO Transfer (CPOL and CPHA bits are changed)
Figure 7 shows the interface timing when extending the setup time. Table 4 and Table 5 list the timing conditions for serial flash memory and the SH7264. Set the RSPI to satisfy these conditions.
MOSI transfer
tCSLS tLEAD SSL00 fSCK tSPcyc RSPCK0 tDS tOD MOSI0 tOH tDH
MISO transfer
tCSH tTD
tCSLH tLAG
tH tV MISO0 tsu tOH
txxx
: Timing conditions for serial flash memory : Timing for latching data
Figure 7 Interface Timing When Extending the Setup Time
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Table 4 Timing Conditions for Serial Flash Memory When Extending the Setup Time Symbol tCSLS Item Chip Select Low Setup Time Description Time required for the slave to latch data from asserting SSL to the RSPCK rising. The following formula must be fulfilled: tLEAD (=RSPCK delay) + 1/2 x tSPcyc > tCSLS (min) Time required for SSL negation. The following formula must be fulfilled: tTD (=2 x B + next access delay) > tCSH (min) The maximum operating frequency supported by the slave. The following formula must be fulfilled: fSCK(max) > 1/ tSPcyc Hold time required from the last RSPCK rising to the SSL negation. The following formula must be fulfilled: tLAG (=SSL negation delay) + 1/2 tSPcyc > tCSLH (min) Time required for the master from outputting data to latching data. The following formula must be fulfilled: tSPcyc - tOD(max) > tDS (min) Time required for the master from latching data to stop the data output. The following formula must be fulfilled: tOH(min) > tDH (min) Related registers SPCKD register SPCMD register
tCSH
Chip Select High Time Serial Clock Frequency
SPND register SPCMD register SPBR register SPCMD register
fSCK
tCSLH
Chip select Low Hold Time
SSLND register SPCMD register
tDS
Data Input Setup Time
tDH
Data Input Hold Time
Table 5 Timing Conditions for the SH7264 MCU when Extending the Setup Time Symbol tSU Item Data Input Setup Time Description Time required for the slave from outputting data to latching data. The following formula must be fulfilled: tSPcyc - tV (max) > tSU (min) Time required for the slave from latching data to stop the data output. The following formula must be fulfilled: tOH(min) > tH(min) Related registers
tH
Data Input Hold Time
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(2)
Extending the Access Width
Specifying the longword-wide access to the Data register (SPDR) reduces the number of times to insert waits (RSPCK delay, SSL negation delay, the next access delay) before and after the transfer to transfer data effectively. When issuing the read command (Opcode: H'0B), the number of bytes output by master (command, address, and dummy data) is five. Therefore, the master outputs and transfers data in byte-wide length, and the slave outputs and transfers data in longword-wide length. The figure below shows an example of the command sequence of the extended access width.
CPOL=1, CPHA=0 Byte-wide access
CPOL = 0, CPHA = 1 Longword-wide access
tLEAD
(tLEAD + tLAG + tTD)
(tLEAD + tLAG + tTD)
tLAG
SSL00 RSPCK0
MOSI0
H'0B
addr1
addr2
addr3
dummy
MISO0
data1
data2
data3
data4
data5
data n
Figure 8 Command Sequence for Longword-wide Access (Opcode: H'0B)
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2.4
2.4.1
Sample Program Operation
RSPI Initialization Example
Figure 9 and Figure 10 show flow charts of initializing the RSPI in the sample program. This setting enables the SPI operation in master mode.
Initialize the RSPI
Set the general-purpose I/O ports (PORT)
* Select the multiplexed pins Function: MISO0, MOSI0, SSL00, RSPCK0 * Enable supplying the clock for the RSPI0
Set the Standby control register 5 (STBCR5)
Set the Control register_0 (SPCR_0)
* Set the SPCR_0 (SPCR_0 = H'00) Function: Disable the RSPI
Set the Pin control register (SPPCR_0)
* Set the SPPCR_0 (SPPCR_0 = H'30) Functions: (1) Set the MOSI idle value to 1 (2) Disable to loop-back * Set the SPBR_0 (SPBR = H'00) Function: Set the bit rate as 36 Mbps (When bus clock is 72 MHz) * Set the SPDCR_0 (SPDCR = H'20) Functions: (1) Disable to transmit the dummy data (2) Set the access width to the SPDR register as 8-bit * Set the SPCKD_0 (SPCKD_0 = H'00) Function: Specify the delay between the SSL signal assertion and the RSPCK oscillation as 1 RSPCK * Set the SSLND_0 (SSLND_0 = H'00) Function: Specify the delay between the RSPCK oscillation stop to the SSL signal negation as 1 RSPCK * Set the SPND_0 (SPND_0 = H'00) Function: Specify the SSL signal negation period after transfer is complete to 1 RSPCK + 2 bus clocks * Set the SPSCR_0 (SPSCR_0 = H'00) Function: Specify the sequence length as 1 (Only the SPCMD register 0 is used)
Set the Bit rate register_0 (SPBR_0)
Set the Data control register_0 (SPDCR_0)
Set the Clock delay register_0 (SPCKD_0)
Set the Slave select negation delay register_0 (SSLND_0)
Set the Next-access delay register_0 (SPND_0)
Set the Sequence control register_0 (SPSCR_0)
A
Figure 9 RSPI Initialization Flow Chart (1/2)
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A
Set the Command register_00 (SPCMD_00)
* Set the SPCMD_00 (SPCMD_00 = H'E780) Functions: (1) Specify the same value in SPCKD_0, SSLND_0, and SPND_0 (2) Specify the data format to MSB first (3) Specify the transfer data length to 8-bit (4) Keep the SSL signal level from the end of the transfer until the beginning of the next access (5) Select the SPBR_0 base bit rate (no division) (6) Specify the RSPCK when idling as 0 (7) Specify the RSPCK to latch data on odd edge, and output data on even edge * Set the SPBFCR_0 (SPBFCR_0 = H'C0, SPBFCR_0 = H'00) Functions: (1) Reset the data in transmit/receive buffers (It should be cleared to 0 every time the data is written) (2) Specify the number of available triggering bytes when the transmit buffer is empty as 1 (3) Specify the number of triggering bytes when the receive buffer is full as 1 * Set the SSLP_0 (SSLP_0 = H'00) Function: Specify the SSL signal to 0-active * Set the SPCR_0 (SPCR_0 = H'48) Functions: (1) Enable the RSPI (2) Disable the transmit, receive, error interrupts (3) Set the RSPI in master mode (4) Disable to detect the mode fault error
Set the Buffer control register_0 (SPBFCR_0)
Set the Slave select polarity register_0 (SSLP_0)
Set the Control register_0 (SPCR_0)
End
Figure 10 RSPI Initialization Flow Chart (2/2)
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2.4.2
Command Transfer Example
The sample program supports two types of command, the Read command that uses both the master output and slave output, and the Write command that uses the master output only. Figure 11 to Figure 13 show the flow charts of the read command transfer. The access width when reading data is specified in longword (32-bit). Use the DMA transfer to store data in memory. Figure 14 shows the flow chart of the write command transfer. As the busy time is longer than the time to transfer commands, the access width is specified in byte-wide in this example.
Read command transfer * Set the SPBFCR register (SPBFCR = 0xC0, SPBFCR = 0x00) Function: Reset the data in the transmit/receive buffers (It should be cleared to 0 every time the data is written.) * Set the SPCR register (SPE bit = 1) Function: Enable the RSPI (This register enables the RSPI transfer function.) * Set the SPCMD register (CPOL bit = 1, CPHA bit = 0) Functions: (1) Specify the RSPCK when idling as 1 (2) Specify the RSPCK to output data on even edge Yes * Transfer data (opcode and address bytes for the command sequence) output by the master. Five bytes in total (opcode 0x0B, three bytes address, and dummy byte) are transferred when the Read Array is issued. * Command size must be equal or less than eight bytes to avoid the transmit FIFO overflow.
Reset the transmit/receive buffers
Enable the SPI to transfer data
Extend the setup time for MOSI direction (Master to Slave)
Transferred all commands? No Write command in the Data register
Wait for the transfer end
Extend the setup time for MISO direction (Slave to Master)
* Set the SPCMD register (CPOL bit = 0, CPHA bit = 1) Functions: (1) Specify the RSPCK when idling as 0 (2) Latch data on odd edge
Reset the transmit/receive buffers
Extend the access width to longword
* Set the SPDCR register (SPLW bit = 3) Function: Specify the access width to the SPDR register as 32-bit * Set the SPCMD register (SPB bit = 3) Function: Specify the transfer data length as 32-bit
B
Figure 11 Flow Chart of the Read Command Transfer (1/3)
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B
Enable the transfer request to DMAC
* Set the SPCR register (SPRIE bit = 1) Function: Enable the RSPI receive interrupt (As this is specified as a factor to activate the DMAC, the interrupt is not requested to CPU.) * Set the CHCR register (H'0000 0000) Function: Disable the DMA transfer * Set the DMARS register (H'0052) Function: Specify the RSPI channel 0 reception as the factor to activate the DMAC * Set the DMAOR register (H'0001) Function: Enable the DMA transfer on all channels * Set the SAR register (Set the SPDR register address) Function: Specify the DMA transfer source address * Set the DAR register Function: Specify the DMA transfer destination address) * Set the DMATCR register Function: Specify the number of the DMA transfers * Set the CHCR register (H'0000 4811) Functions: (1) Specify the DMA transfer to stop when the TE bit is set (2) Increment the destination address (3) Fix the source address (4) Specify the DMA extension selector as the transfer request source (5) Specify the transfer bus mode as the cycle steal mode (6) Specify the transfer size in units of longword (7) Disable the interrupt request (8) Enable the DMA transfer
Set the DMA transfer
C
Figure 12 Flow Chart of the Read Command Transfer (2/3)
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C
Start to transmit dummy data
* Set the SPDCR register (TXDMY bit = 1) Function: Enable the SPI to transmit dummy data (The dummy data is automatically sent when not writing data in the Data register.)
No
DMA transfer is completed? Yes Stop transmitting the dummy data
Disable the DMA transfer
Wait for the transfer end
* Make sure the transfer is complete before clearing the SPE bit.
Disable the SPI to transfer data
* Set the SPCR register (SPE bit = 0) Function: Disable the RSPI SSL signal is negated by this setting. As the RSPI control bit is not initialized, reset the SPE bit to 1 to activate the RSPI in the same transfer mode. * Set the SPDCR register (SPLW bit = 1) Function: Specify the access width to the SPDR register as 8-bit * Set the SPCMD register (SPB bit = 7) Function: Specify the transfer data length as 8-bit
Reset the access width in bytes
End
Figure 13 Flow Chart of the Read Command Transfer (3/3)
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Write command transfer * Set the SPBFCR register (SPBFCR = H'C0, SPBFCR = H'00) Function: Reset the data in the transmit/receive buffer (It should be cleared to 0 every time the data is written) * Set the SPCR register (SPE bit = 1) Function: Enable the RSPI This register enables the RSPI transfer function. As there is a register not allowing to rewrite data when SP bit is 1, pay close attention when setting this register. The Command register (SPCMD) does not restrict the the SPE bit value when the TEND bit is 1. * Set the SPCMD register (CPOL bit = 1, CPHA bit = 0) Functions: (1) Specify the RSPCK when idling as 1 (2) Output data on even edge Yes * Transfer data (opcode and address bytes for command sequence) output by the master
Reset the transmit/receive buffers
Enable the SPI to transfer data
Extend the setup time for MOSI direction (Master to Slave)
Transferred all commands? No Write command in the Data register
* Command size must be equal or less than eight bytes to avoid the transmit FIFO overflow.
Transferred all data to write? No No
Yes
Transmit FIFO is empty? Yes Write data in the Data register
No
Any data exists in the receive FIFO? Yes Read the Data register * Read the dummy data as the RSPI transfer stops when the receive FIFO overflows upon the RSPI is operating as the master.
Wait for the transfer end
Disable the SPI to transfer data
* Set the SPCR register (SPE bit = 0) Function: Disable the RSPI This register disables the RSPI transfer function. The SSL signal is negated by this setting.
End
Figure 14 Flow Chart of the Write Command Transfer
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2.4.3 Main Function
The figure below shows the flow chart of the main function in the sample program. The sample program writes data in the entire memory array, and compares the written value to the read value.
Main function Initialize the RSPI * To access serial flash memory, initialize the RSPI as described in 2.4.1 RSPI Initialization Example. * Unprotect serial flash memory using the Write Status Register command (H'01). * Erase the entire memory array in serial flash memory using the Chip Erase command (H'C7). Writing in all sectors completed? No Generate one sector write data (64 KB) Yes
Unprotect serial flash memory
Erase the entire memory array
Write one page (256 bytes) data in serial flash memory
* Execute the Byte/Page Program command (H'02). As the Byte/Page program command cannot write data more than the size of one page (256 bytes), continue to execute this command to write in the entire memory array.
No
Writing one sector data completed? Yes
Reading all sectors completed? No
Yes
Read one sector (64 KB) data from serial flash memory (note) * Execute the Read Array command (H'0B). As this command reads the entire memory array continuously, the command reads data in sectors in this application. Specify the access width to the Data register (SPDR) in longword.
Compare the written data value with the provided data
Verify OK? Yes
No
Display an error
Protect serial flash memory
Note: When using the DMA transfer, cache coherency must be maintained by software. This sample program assigns the transfer destination buffer in cache-disabled space.
Figure 15 Main Function Flow Chart
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3. 3.1
Sample Program Listing Sample Program Listing "main.c" (1/3)
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 /****************************************************************************** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * OS Version Device Tool-Chain Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of this software. By using this software, you agree to the additional terms and conditions found by accessing the following link: http://www.renesas.com/disclaimer Copyright (C) 2009. Renesas Technology Corp., All Rights Reserved. System Name : SH7264 Sample Program File Name Abstract : main.c : High-speed Read/Write Serial Flash Memory : Using the Renesas Serial Peripheral Interface : 1.00.00 : SH7262/SH7264 : High-performance Embedded Workshop (Ver.4.04.01). : C/C++ compiler package for the SuperH RISC engine family : : None H/W Platform: M3A-HS64G50 (CPU board) Description : History : Apr.21,2009 Ver.1.00.00 (Ver.9.02 Release00). TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS TECHNOLOGY CORP. NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THE THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. DISCLAIMED. ALL SUCH WARRANTIES ARE EXPRESSLY This software is owned by Renesas Technology Corp. and is protected under all applicable laws, including copyright laws. This software is supplied by Renesas Technology Corp. and is only intended for use with Renesas products. No other uses are authorized. DISCLAIMER
******************************************************************************** *""FILE COMMENT""*********** Technical reference data **************************
******************************************************************************** *""FILE COMMENT END""**********************************************************/
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Sample Program Listing "main.c" (2/3)
#include #include "serial_flash.h" /* ==== Macro definition ==== */ #define TOP_ADDRESS 0 /* Start address of serial flash memory */
/* ==== Function prototype declaration ==== */ void main(void); /* ==== Variable definition ==== */ #pragma section LARGE_ONCHIP_RAM static unsigned char data[SF_SECTOR_SIZE]; static unsigned long rbuf[SF_SECTOR_SIZE/sizeof(long)]; #pragma section /*""FUNC COMMENT""************************************************************** * ID * Outline * Include * Declaration * Description * * * * Argument : : Accessing serial flash memory main : "serial_flash.h" : void main(void); : Erases, programs, and reads serial flash memory. : After initializing the RSPI channel 0, erases the entire memory : array, and writes data from the start address. Reads the : written data to compare to the provided data. : void
*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------*------------------------------------------------------------------------------
*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------* Return Value : void *-----------------------------------------------------------------------------* Note void main(void) { int i, j; unsigned char *p; static unsigned long addr; /* ==== Initializes the RSPI ==== */ sf_init_serial_flash(); /* ==== Unprotects serial flash memory ==== */ sf_protect_ctrl( SF_REQ_UNPROTECT ); : None *""FUNC COMMENT END""**********************************************************/
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Sample Program Listing "main.c" (3/3)
/* ==== Chip erase (2 MB, it takes about 10 seconds to complete) ==== */ sf_chip_erase(); /* ==== Writes data (2 MB, it takes about 10 seconds to complete) ==== */ addr = TOP_ADDRESS; for(i = 0; i < SF_NUM_OF_SECTOR; i++){ /* ---- Initializes the data (64 KB) ---- */ for(j = 0; j < SF_SECTOR_SIZE; j++){ data[j] = (i + j) % 100; } /* ---- Writes one sector (64 KB) data ---- */ for(j = 0; j < ( SF_SECTOR_SIZE / SF_PAGE_SIZE ); j++){ /* ---- Writes one page (256 bytes) data ---- */ sf_byte_program( addr, data+(j*SF_PAGE_SIZE), SF_PAGE_SIZE ); addr += SF_PAGE_SIZE; } } /* ==== Reads data (2 MB) ==== */ addr = TOP_ADDRESS; for(i = 0; i < SF_NUM_OF_SECTOR; i++){ /* ---- Reads one sector (64 KB) data ---- */ sf_byte_read_long( addr, rbuf, SF_SECTOR_SIZE ); addr += SF_SECTOR_SIZE; /* ---- Verifies data ---- */ p = (unsigned char *)rbuf; for(j = 0; j < SF_SECTOR_SIZE; j++){ data[j] = (i + j) % 100; if( data[j] != *(p+j) ){ puts("Error: verify error\n"); fflush(stdout); while(1); } } } /* ==== Protects serial flash memory ==== */ sf_protect_ctrl( SF_REQ_PROTECT ); while(1){ /* loop */ } } /* End of File */ /* Outputs the written data */ /* Updates the source address to read */ /* Updates the destination address to write */
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Sample Program Listing "serial_flash.c" (1/19)
/****************************************************************************** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * OS Version Device Tool-Chain Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of this software. By using this software, you agree to the additional terms and conditions found by accessing the following link: http://www.renesas.com/disclaimer Copyright (C) 2009. Renesas Technology Corp., All Rights Reserved. System Name : SH7264 Sample Program File Name Abstract : serial_flash.c : High-speed Read/Write Serial Flash Memory : Using the Renesas Serial Peripheral Interface : 1.00.00 : SH7262/SH7264 : High-performance Embedded Workshop (Ver.4.04.01). : C/C++ compiler package for the SuperH RISC engine family : : None H/W Platform: M3A-HS64G50 (CPU board) Description : History : Mar.09,2009 Ver.1.00.00 (Ver.9.02 Release00). TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS TECHNOLOGY CORP. NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THE THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. DISCLAIMED. ALL SUCH WARRANTIES ARE EXPRESSLY This software is owned by Renesas Technology Corp. and is protected under all applicable laws, including copyright laws. This software is supplied by Renesas Technology Corp. and is only intended for use with Renesas products. No other uses are authorized. DISCLAIMER
******************************************************************************** *""FILE COMMENT""*********** Technical reference data **************************
******************************************************************************** *""FILE COMMENT END""**********************************************************/ #include #include #include "iodefine.h" #include "serial_flash.h"
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49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 /*""FUNC COMMENT""************************************************************** * ID * Outline * Include * Declaration * Description * * * Argument : : Serial flash memory initialization : : void sf_init_serial_flash(void); : Initializes serial flash memory for being accessed. : Initializes channel 0 of the Renesas Serial Peripheral : Interface (RSPI). : void /* ==== Variable definition ==== */ /* ==== Function prototype declaration ==== */ /*** Local function ***/ static void write_enable(void); static void write_disable(void); static void busy_wait(void); static unsigned char read_status(void); static void write_status(unsigned char status); static void io_init_rspi(void); static void io_cmd_exe(unsigned char *ope, int ope_sz, unsigned char *data, int data_sz); static void io_cmd_exe_rdmode(unsigned char *ope, int ope_sz, unsigned char *rd, int rd_sz);
static void io_cmd_exe_rdmode_cpu_l(unsigned char *ope, int ope_sz, unsigned long *rd, int rd_sz); static void io_cmd_exe_rdmode_dma_l(unsigned char *ope, int ope_sz, unsigned long *rd, int rd_sz);
Sample Program Listing "serial_flash.c" (2/19)
/* ==== Macro definition ==== */ #define SFLASHCMD_CHIP_ERASE 0xc7 #define SFLASHCMD_SECTOR_ERASE 0xd8 #define SFLASHCMD_BYTE_PROGRAM 0x02 #define SFLASHCMD_BYTE_READ #define SFLASHCMD_BYTE_READ_LOW #define SFLASHCMD_WRITE_DISABLE 0x0B 0x03 0x04
#define SFLASHCMD_WRITE_ENABLE 0x06 #define SFLASHCMD_READ_STATUS 0x05 #define SFLASHCMD_WRITE_STATUS 0x01 #define UNPROTECT_WR_STATUS #define PROTECT_WR_STATUS #define SF_USE_DMAC 0x00 0x3C /* Define this macro when using the function (sf_byte_read_long)in the DMA transfer */
static void io_wait_tx_end(void);
*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------*------------------------------------------------------------------------------
*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------* Return Value : void *-----------------------------------------------------------------------------* Note : None *""FUNC COMMENT END""**********************************************************/
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Sample Program Listing "serial_flash.c" (3/19)
void sf_init_serial_flash(void) { /* ==== Initializes the RSPI0 ==== */ io_init_rspi(); } /*""FUNC COMMENT""************************************************************** * ID * Outline * Include * Declaration * Description * * * Argument * : : Protect/unprotect operation : "serial_flash.h" : void sf_init_serial_flash(void); : Protects or unprotects serial flash memory. : Use the argument req to specify. Default setting and unprotecting : method depends on the specifications of the serial flash memory. : enum sf_req req ; I : SF_REQ_UNPROTECT -> Write-enable all sectors : SF_REQ_PROTECT -> Write-protect all sectors
*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------*------------------------------------------------------------------------------
*------------------------------------------------------------------------------
*-----------------------------------------------------------------------------* Return Value : void *-----------------------------------------------------------------------------* Note : None *""FUNC COMMENT END""**********************************************************/ void sf_protect_ctrl(enum sf_req req) { if( req == SF_REQ_UNPROTECT ){ write_status( UNPROTECT_WR_STATUS); } else{ write_status( PROTECT_WR_STATUS ); } } /* Protects total area */ /* Unprotects total area */
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Sample Program Listing "serial_flash.c" (4/19)
/*""FUNC COMMENT""************************************************************** * ID * Outline * Include * Declaration * Description * * * * Argument : : Chip erase : : void sf_chip_erase(void); : Erases all bits in serial flash memory. : Before erasing or programming, issue the Write Enable command. : After erasing or programming, make sure to check the status of : serial flash memory if it is not busy. : void
*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------*------------------------------------------------------------------------------
*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------* Return Value : void *-----------------------------------------------------------------------------* Note : None *""FUNC COMMENT END""**********************************************************/ void sf_chip_erase(void) { unsigned char cmd[1]; cmd[0] = SFLASHCMD_CHIP_ERASE; write_enable(); io_cmd_exe(cmd, 1, NULL, 0); busy_wait(); } /*""FUNC COMMENT""************************************************************** * ID * Outline * Include * Declaration * Description * * * * Argument : : Sector erase : : void sf_sector_erase(void); : Erases the specified sector in serial flash memory. : Before erasing or programming, issue the Write Enable command. : After erasing or programming, make sure to check the status of : serial flash memory if it is not busy. : int sector_no ; I : Sector number
*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------*------------------------------------------------------------------------------
*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------* Return Value : void *-----------------------------------------------------------------------------* Note : None *""FUNC COMMENT END""**********************************************************/
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Sample Program Listing "serial_flash.c" (5/19)
void sf_sector_erase(int sector_no) { unsigned char cmd[4]; unsigned long addr = sector_no * SF_SECTOR_SIZE; cmd[0] = SFLASHCMD_SECTOR_ERASE; cmd[1] = (addr >> 16) & 0xff; cmd[2] = (addr >> cmd[3] = addr 8) & 0xff; & 0xff;
write_enable(); io_cmd_exe(cmd, 4, NULL, 0); busy_wait(); } /*""FUNC COMMENT""************************************************************** * ID * Outline * Include * Declaration * Description * * * * * Argument * * : : Program data : : void sf_byte_program(unsigned long addr, unsigned char *buf, int size); : Programs the specified data in serial flash memory. : Before erasing or programming, issue the Write Enable command. : After erasing or programming, make sure to check the status of : serial flash memory if it is not busy. : The maximum write data size depends on the type of the device. : unsigned long addr ; I : Address in serial flash memory to write : unsigned char *buf ; I : Buffer address to store the write data : int size ; I : Number of bytes to write
*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------*------------------------------------------------------------------------------
*------------------------------------------------------------------------------
*-----------------------------------------------------------------------------* Return Value : void *-----------------------------------------------------------------------------* Note : None *""FUNC COMMENT END""**********************************************************/ void sf_byte_program(unsigned long addr, unsigned char *buf, int size) { unsigned char cmd[4]; cmd[0] = SFLASHCMD_BYTE_PROGRAM; cmd[1] = (unsigned char)((addr >> 16) & 0xff); cmd[2] = (unsigned char)((addr >> cmd[3] = (unsigned char)( addr write_enable(); io_cmd_exe(cmd, 4, buf, size); busy_wait(); } 8) & 0xff); & 0xff);
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Sample Program Listing "serial_flash.c" (6/19)
/*""FUNC COMMENT""************************************************************** * ID * Outline * Include * Declaration * Description * Argument * * : : Read data (byte transfer). : : void sf_byte_read(unsigned long addr, unsigned char *buf, int size); : Reads the specified number of bytes from serial flash memory. : unsigned long addr ; I : Address in serial flash memory to read : unsigned char *buf ; I : Buffer address to store the read data : int size ; I : Number of bytes to read
*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------*------------------------------------------------------------------------------
*-----------------------------------------------------------------------------* Return Value : void *-----------------------------------------------------------------------------* Note : None *""FUNC COMMENT END""**********************************************************/ void sf_byte_read(unsigned long addr, unsigned char *buf, int size) { unsigned char cmd[5]; cmd[0] = SFLASHCMD_BYTE_READ; cmd[1] = (unsigned char)((addr >> 16) & 0xff); cmd[2] = (unsigned char)((addr >> cmd[3] = (unsigned char)( addr cmd[4] = 0x00; io_cmd_exe_rdmode(cmd, 5, buf, size); } /*""FUNC COMMENT""************************************************************** * ID * Outline * Include * Declaration * Description * * Argument * * : : Read data (Longword transfer). : : void sf_byte_read_long(unsigned long addr, unsigned long *buf, int size); : Reads the specified number of bytes in units of longword : from serial flash memory. : unsigned long addr ; I : Address in serial flash memory to read : unsigned long *buf ; I : Buffer address to store the read data : int size ; I : Number of bytes to read 8) & 0xff); & 0xff);
*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------*------------------------------------------------------------------------------
*------------------------------------------------------------------------------
*-----------------------------------------------------------------------------* Return Value : void *-----------------------------------------------------------------------------* Note : None *""FUNC COMMENT END""**********************************************************/
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Sample Program Listing "serial_flash.c" (7/19)
void sf_byte_read_long(unsigned long addr, unsigned long *buf, int size) { unsigned char cmd[5]; cmd[0] = SFLASHCMD_BYTE_READ; cmd[1] = (unsigned char)((addr >> 16) & 0xff); cmd[2] = (unsigned char)((addr >> cmd[3] = (unsigned char)( addr cmd[4] = 0x00; #ifdef SF_USE_DMAC io_cmd_exe_rdmode_dma_l(cmd, 5, buf, size); #else io_cmd_exe_rdmode_cpu_l(cmd, 5, buf, size); #endif } /*""FUNC COMMENT""************************************************************** * ID * Outline * Include * Declaration * Description * * Argument : : Write enable : : static void write_enable(void); : Issues the Write Enable command to enable erasing or programming : serial flash memory. : void 8) & 0xff); & 0xff);
*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------*------------------------------------------------------------------------------
*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------* Return Value : void *-----------------------------------------------------------------------------* Note : None *""FUNC COMMENT END""**********************************************************/ static void write_enable(void) { unsigned char cmd[1]; cmd[0] = SFLASHCMD_WRITE_ENABLE; io_cmd_exe(cmd, 1, NULL, 0); }
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Sample Program Listing "serial_flash.c" (8/19)
/*""FUNC COMMENT""************************************************************** * ID * Outline * Include * Declaration * Description * * Argument : : Write disable : : static void write_disable(void); : Issues the Write Disable command to disable erasing or programming : serial flash memory. : void
*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------*------------------------------------------------------------------------------
*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------* Return Value : void *-----------------------------------------------------------------------------* Note : None *""FUNC COMMENT END""**********************************************************/ static void write_disable(void) { unsigned char cmd[1]; cmd[0] = SFLASHCMD_WRITE_DISABLE; io_cmd_exe(cmd, 1, NULL, 0); } /*""FUNC COMMENT""************************************************************** * ID * Outline * Include * Declaration * Description * Argument : : Busy wait : : static void busy_wait(void); : Loops internally when the serial flash memory is busy. : void
*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------* Return Value : void *-----------------------------------------------------------------------------* Note : None *""FUNC COMMENT END""**********************************************************/ static void busy_wait(void) { while ((read_status() & 0x01) != 0) { /* serial flash is busy */ } } /* RDY/BSY */
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Sample Program Listing "serial_flash.c" (9/19)
/*""FUNC COMMENT""************************************************************** * ID * Outline * Include * Declaration * Description * Argument : : Read status : : static unsigned char read_status(void); : Reads the status of serial flash memory. : void
*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------* Return Value : Status register value *-----------------------------------------------------------------------------* Note : None *""FUNC COMMENT END""**********************************************************/ static unsigned char read_status(void) { unsigned char buf; unsigned char cmd[1]; cmd[0] = SFLASHCMD_READ_STATUS; io_cmd_exe_rdmode(cmd, 1, &buf, 1); return buf; } /*""FUNC COMMENT""************************************************************** * ID * Outline * Include * Declaration * Description * Argument : : Write status : : static void write_status(unsigned char status); : Writes the status of serial flash memory. : unsigned char status ; I : status register value
*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------* Return Value : void *-----------------------------------------------------------------------------* Note : None *""FUNC COMMENT END""**********************************************************/ static void write_status(unsigned char status) { unsigned char cmd[2]; cmd[0] = SFLASHCMD_WRITE_STATUS; cmd[1] = status;
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Sample Program Listing "serial_flash.c" (10/19)
write_enable(); io_cmd_exe(cmd, 2, NULL, 0); busy_wait(); } /*""FUNC COMMENT""************************************************************** * ID * Outline * Include * Declaration * Description * * * Argument : : RSPI initialization : : static void io_init_rspi(void); : Initializes channel 0 of the RSPI. : Sets the RSPI in master mode to set parameters to transfer : according to the specifications of serial flash memory. : void
*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------*------------------------------------------------------------------------------
*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------* Return Value : void *-----------------------------------------------------------------------------* Note : None *""FUNC COMMENT END""**********************************************************/ static void io_init_rspi(void) { /* ==== PORT ==== */ PORT.PFCR3.BIT.PF12MD = 3; PORT.PFCR2.BIT.PF11MD = 3; PORT.PFCR2.BIT.PF10MD = 3; PORT.PFCR2.BIT.PF9MD /* ==== CPG ==== */ CPG.STBCR5.BIT.MSTP51 = 0; /* RSPI0 active */ = 3; /* PF12:MISO0 */ /* PF11:MOSI0 */ /* PF10:SSL00 */ /* PF9:RSPCK0 */
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Sample Program Listing "serial_flash.c" (11/19)
/* ==== RSPI ==== */ RSPI0.SPCR.BYTE RSPI0.SPPCR.BYTE RSPI0.SPBR.BYTE RSPI0.SPDCR.BYTE RSPI0.SPCKD.BYTE RSPI0.SSLND.BYTE RSPI0.SPND.BYTE RSPI0.SPSCR.BYTE = 0x00; = 0x30; = 0x00; = 0x20; = 0x00; = 0x00; = 0x00; = 0x00; /* Disables channel 0 of the RSPI */ /* MOSI idle fixed value = 1 */ /* Specifies the base bit rate as 36 MHz (Bus clock = 72 MHz) */ /* Disables to transmit the dummy data */ /* RSPCK delay: 1 RSPCK */ /* SSL negate delay: 1 RSPCK */ /* Next access delay: 1 RSPCK + 2 Bus clocks */ /* Sequence length: 1 (SPCMD0 is only used) */ /* Access width to the SPDR register: 8-bit */
RSPI0.SPCMD0.WORD = 0xE780; /* MSB first */ /* Data length: 8-bit */ /* Keeps the SSL signal level after transfer is completed */ /* Bit rate: Base bit rate is not divided */ /* RSPCK when idling is 0 */ /* Latches data on odd edge, outputs data on even edge */ RSPI0.SPBFCR.BYTE = 0xC0; RSPI0.SPBFCR.BYTE = 0x00; /* Enables to reset data in the /* Disables to reset data in the transmit/receive buffer */ transmit/receive buffer */ /* Number of triggers in transmit buffer: more than one byte available */ /* Number of triggers in receive buffer: more than one byte received */ RSPI0.SSLP.BYTE RSPI0.SPCR.BYTE = 0x00; = 0x48; /* SSLP = b'0 SSL signal 0-active */ /* Master mode */
/* Disables interrupts */ /* Enables channel 0 of the RSPI */ }
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Sample Program Listing "serial_flash.c" (12/19)
/*""FUNC COMMENT""************************************************************** * ID * Outline * Include * Declaration * * Description * * * * * Argument * * * * * : int data_sz : int ope_sz : : Execute command (No read data). : : static void io_cmd_exe(unsigned char *ope, int ope_sz, : unsigned char *data,int data_sz)
*-----------------------------------------------------------------------------*------------------------------------------------------------------------------
*-----------------------------------------------------------------------------: Executes the specified command. : Transmits the argument ope, and then transmits the argument data. : Discards the received data. : Set one of the values between 0 and 8 in the ope_sz. : Set one of the values between 0 and 256 in the data_sz. : unsigned char *ope ; I : Start address of the opcode block and address block to transmit ; I : Number of bytes in the opcode block and address block : unsigned char *data; I : Start address of the data block to transmit ; I : Number of bytes in the data block
*------------------------------------------------------------------------------
*-----------------------------------------------------------------------------* Return Value : void *-----------------------------------------------------------------------------* Note : None *""FUNC COMMENT END""**********************************************************/ static void io_cmd_exe(unsigned char *ope, int ope_sz, unsigned char *data, int data_sz) { unsigned char tmp; /* ==== Resets buffer ==== */ RSPI0.SPBFCR.BYTE RSPI0.SPBFCR.BYTE = 0xC0u; = 0x00u;
/* ---- Enables the SPI transfer ---- */ RSPI0.SPCR.BIT.SPE = 1; /* ==== MOSI (command, address, write data) ==== */ RSPI0.SPCMD0.BIT.CPOL= 1; RSPI0.SPCMD0.BIT.CPHA= 0; while(ope_sz--){ RSPI0.SPDR.BYTE = *ope++; /* Command size must be equal or less than 8 bytes */ } /* RSPCK when idling is 1 */ /* Outputs data on even (rising) edge */
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Sample Program Listing "serial_flash.c" (13/19)
while(data_sz--){ while( RSPI0.SPSR.BIT.SPTEF == 0 ){ /* wait */ } RSPI0.SPDR.BYTE = *data++; if( RSPI0.SPSR.BIT.SPRF == 1 ){ tmp = RSPI0.SPDR.BYTE; /* Dummy read to avoid an overflow of data */ } } io_wait_tx_end(); /* Waits for transfer end */
/* ---- SPI transfer end (SSL negation) ---- */ RSPI0.SPCR.BIT.SPE = 0; } /*""FUNC COMMENT""************************************************************** * ID * Outline * Include * Declaration * * Description * * * * * Argument * * * * * : unsigned char *rd : int rd_sz : int ope_sz : : Execute command (With read data, byte transfer). : : static void io_cmd_exe_rdmode(unsigned char *ope, int ope_sz, : unsigned char *rd, int rd_sz)
*-----------------------------------------------------------------------------*------------------------------------------------------------------------------
*-----------------------------------------------------------------------------: Executes the specified command. : Transmits the argument ope, and then receives data in the argument rd. : Transfer data in unit of bytes. : Set one of the values between 0 and 8 in the ope_sz. : More than 0 can be set in the rd_sz. : unsigned char *ope ; I : Start address of the opcode block and address block to transmit ; I : Number of bytes in the opcode block and address block ; I : Buffer address to store the received data ; I : Number of bytes in the data block
*------------------------------------------------------------------------------
*-----------------------------------------------------------------------------* Return Value : void *-----------------------------------------------------------------------------* Note : None *""FUNC COMMENT END""**********************************************************/ static void io_cmd_exe_rdmode(unsigned char *ope, int ope_sz, unsigned char *rd, int rd_sz) { /* ==== Resets buffer ==== */ RSPI0.SPBFCR.BYTE RSPI0.SPBFCR.BYTE = 0xC0u; = 0x00u;
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Sample Program Listing "serial_flash.c" (14/19)
/* ---- Enables the SPI transfer ---- */ RSPI0.SPCR.BIT.SPE = 1; /* ---- MOSI (command, address, dummy) ---- */ RSPI0.SPCMD0.BIT.CPOL= 1; RSPI0.SPCMD0.BIT.CPHA= 0; while(ope_sz--){ RSPI0.SPDR.BYTE = *ope++; /* Command size must be equal or less than 8 bytes */ } io_wait_tx_end(); /* Waits for transfer end */ /* RSPCK when idling is 1 */ /* Outputs data on even (rising) edge */
/* ---- MISO (read data) ---- */ RSPI0.SPCMD0.BIT.CPOL= 0; RSPI0.SPCMD0.BIT.CPHA= 1; RSPI0.SPBFCR.BYTE RSPI0.SPBFCR.BYTE = 0xC0u; = 0x00u; /* Enables to transmit the dummy data */ /* RSPCK when idling is 0 */ /* Latches data on even (falling) edge */ /* Resets buffer */
RSPI0.SPDCR.BIT.TXDMY = 1; while(rd_sz--){
while( RSPI0.SPSR.BIT.SPRF == 0){ /* wait */ } *rd++ = RSPI0.SPDR.BYTE; } RSPI0.SPDCR.BIT.TXDMY = 0; io_wait_tx_end(); /* Disables to transmit the dummy data */ /* Waits for transfer end */
/* ---- SPI transfer end (SSL negation) ---- */ RSPI0.SPCR.BIT.SPE = 0; }
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Sample Program Listing "serial_flash.c" (15/19)
/*""FUNC COMMENT""************************************************************** * ID * Outline * Include * Declaration * * Description * * * * * * Argument * * * * * : unsigned long *rd : int rd_sz : int ope_sz : : Execute command (With read data, longword transfer). : : static void io_cmd_exe_rdmode_cpu_l(unsigned char *ope, int ope_sz, : : Executes the specified command. : Transmits the argument ope, and then receives data in the argument rd. : Transfer the read data in units of longword. : Set one of the values between 0 and 8 in the ope_sz. : Although more than 0 can be set in the rd_sz, set the value : in multiples of 4. : unsigned long *ope ; I : Start address of the opcode block and address block to transmit ; I : Number of bytes in the opcode block and : address block ; I : Buffer address to store the received data ; I : Number of bytes in the data block unsigned long *rd, int rd_sz);
*-----------------------------------------------------------------------------*------------------------------------------------------------------------------
*------------------------------------------------------------------------------
*------------------------------------------------------------------------------
*-----------------------------------------------------------------------------* Return Value : void *-----------------------------------------------------------------------------* Note : None *""FUNC COMMENT END""**********************************************************/ static void io_cmd_exe_rdmode_cpu_l(unsigned char *ope, int ope_sz, unsigned long *rd, int rd_sz) { /* ==== Resets buffer ==== */ RSPI0.SPBFCR.BYTE RSPI0.SPBFCR.BYTE = 0xC0u; = 0x00u;
/* ---- Enables the SPI transfer ---- */ RSPI0.SPCR.BIT.SPE = 1; /* ---- MOSI (command, address, dummy) ---- */ RSPI0.SPCMD0.BIT.CPOL= 1; RSPI0.SPCMD0.BIT.CPHA= 0; while(ope_sz--){ RSPI0.SPDR.BYTE = *ope++; /* Command size must be equal or less than 8 bytes */ } io_wait_tx_end(); /* Waits for transfer end */ /* RSPCK when idling is 1 */ /* Outputs data on even (rising) edge */
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Sample Program Listing "serial_flash.c" (16/19)
/* ---- MISO (read data) ---- */ RSPI0.SPCMD0.BIT.CPOL= 0; RSPI0.SPCMD0.BIT.CPHA= 1; RSPI0.SPBFCR.BYTE RSPI0.SPBFCR.BYTE = 0xC0u; = 0x00u; /* Access width to the SPDR register: 32-bit */ /* Transfer data length: 32-bit */ /* Enables to transmit the dummy data */ /* Calculates the number of transfers in longword */ /* RSPCK when idling is 0 */ /* Latches data on even (falling) edge */ /* Resets buffer */
RSPI0.SPDCR.BIT.SPLW = 3; RSPI0.SPCMD0.BIT.SPB = 3; RSPI0.SPDCR.BIT.TXDMY = 1; rd_sz >>= 2; while( rd_sz-- ){
while( RSPI0.SPSR.BIT.SPRF == 0){ /* wait */ } *rd++ = RSPI0.SPDR.LONG; } RSPI0.SPDCR.BIT.TXDMY = 0; io_wait_tx_end(); /* Disables to transmit the dummy data */ /* Waits for transfer end */
/* ==== Restores the SPI to default setting ==== */ RSPI0.SPCR.BIT.SPE = 0; RSPI0.SPDCR.BIT.SPLW = 1; RSPI0.SPCMD0.BIT.SPB = 7; } #ifdef SF_USE_DMAC /* Access width to the SPDR register: 8-bit */ /* Transfer data length: 8-bit */
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Sample Program Listing "serial_flash.c" (17/19)
/*""FUNC COMMENT""************************************************************** * ID * Outline * Include * Declaration * * Description * * * * * * Argument * * * * * : unsigned long *rd : int rd_sz : int ope_sz : : Execute command (With read data, longword transfer and DMA). : : static void io_cmd_exe_rdmode_dma_l(unsigned char *ope, int ope_sz, : : Executes the specified command. : Transmits the argument ope, and then receives data in the argument rd. : Transfer the read data in units of longword, by the DMA transfer. : Set one of the values between 0 and 8 in the ope_sz. : Although more than 0 can be set in the rd_sz, set the value : in multiples of 4. : unsigned long *ope ; I : Start address of the opcode block and address block ; I : Number of bytes in the opcode block and address block ; I : Buffer address to store the received data ; I : Number of bytes in the data block unsigned long *rd, int rd_sz);
*-----------------------------------------------------------------------------*------------------------------------------------------------------------------
*------------------------------------------------------------------------------
*------------------------------------------------------------------------------
*-----------------------------------------------------------------------------* Return Value : void *-----------------------------------------------------------------------------* Note : None *""FUNC COMMENT END""**********************************************************/ static void io_cmd_exe_rdmode_dma_l(unsigned char *ope, int ope_sz, unsigned long *rd, int rd_sz) { /* ==== Resets buffer ==== */ RSPI0.SPBFCR.BYTE RSPI0.SPBFCR.BYTE = 0xC0u; = 0x00u;
/* ---- Enables the SPI transfer ---- */ RSPI0.SPCR.BIT.SPE = 1; /* ---- MOSI (command, address, dummy) ---- */ RSPI0.SPCMD0.BIT.CPOL= 1; RSPI0.SPCMD0.BIT.CPHA= 0; while(ope_sz--){ RSPI0.SPDR.BYTE = *ope++; /* Command size must be equal or less than 8 bytes */ } io_wait_tx_end(); /* Waits for transfer end */ /* RSPCK when idling is 1 */ /* Outputs data on even (rising) edge */
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Sample Program Listing "serial_flash.c" (18/19)
/* ==== MISO (read data) ==== */ RSPI0.SPCMD0.BIT.CPOL= 0; RSPI0.SPCMD0.BIT.CPHA= 1; RSPI0.SPBFCR.BYTE RSPI0.SPBFCR.BYTE = 0xC0u; = 0x00u; /* Access width to the SPDR register: 32-bit */ /* Transfer data length: 32-bit */ /* RSPCK when idling is 0 */ /* Latches data on even (falling) edge */ /* Resets buffer */
RSPI0.SPDCR.BIT.SPLW = 3; RSPI0.SPCMD0.BIT.SPB = 3;
/* ---- Enables the DMA transfer ---- */ RSPI0.SPCR.BIT.SPRIE = DMAC.CHCR0.LONG DMAC.DMARS0.WORD = DMAC.DMAOR.WORD DMAC.SAR0.LONG DMAC.DAR0.LONG DMAC.DMATCR0.LONG DMAC.CHCR0.LONG = = = = = = 1; /* Enable an interrupt (for DMA transfer) */ /* RSPI0 Rx */ /* Enables all DMA transfers */ /* Transfer destination address */ /* Transfer size */ /* Transfer size (long), enables the DMA transfer */ /* ---- Receives data ---- */ RSPI0.SPDCR.BIT.TXDMY = 1; while(DMAC.CHCR0.BIT.TE == 0){ /* wait */ } RSPI0.SPDCR.BIT.TXDMY = 0; DMAC.CHCR0.LONG io_wait_tx_end(); = 0x00000000ul; /* Disables to transmit the dummy data */ /* Disables the DMA0 */ /* Waits for transfer end */ /* Enables to transmit the dummy data */ /* Waits for the DMA transfer end */ 0x00000000; /* Disables the DMA transfer */ 0x0001u;
0x0052u;
(unsigned long)&(RSPI0.SPDR.BYTE); (unsigned long)rd; rd_sz >> 2; (unsigned long)0x00004811;
/* ==== Restores the SPI to default setting ==== */ RSPI0.SPCR.BIT.SPE = 0; RSPI0.SPDCR.BIT.SPLW = 1; RSPI0.SPCMD0.BIT.SPB = 7; } #endif /* SF_USE_DMAC */ /* Access width to the SPDR register: 8-bit */ /* Transfer data length: 8-bit */
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Sample Program Listing "serial_flash.c" (19/19)
/*""FUNC COMMENT""************************************************************** * ID * Outline * Include * Declaration * Description * Argument : : Transfer end wait : : static void io_wait_tx_end(void); : Loops internally until the transmission is completed. : void
*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------*-----------------------------------------------------------------------------* Return Value : void *-----------------------------------------------------------------------------* Note : None *""FUNC COMMENT END""**********************************************************/ static void io_wait_tx_end(void) { while(RSPI0.SPSR.BIT.TEND == 0){ /* wait */ } } /* End of File */
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Sample Program Listing "serial_flash.h" (1/2)
/****************************************************************************** * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * * OS Version Device Tool-Chain Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of this software. By using this software, you agree to the additional terms and conditions found by accessing the following link: http://www.renesas.com/disclaimer Copyright (C) 2009. Renesas Technology Corp., All Rights Reserved. System Name : SH7264 Sample Program File Name Abstract : serial_flash.h : High-speed Read/Write Serial Flash Memory : Using the Renesas Serial Peripheral Interface : 1.00.00 : SH7262/SH7264 : High-performance Embedded Workshop (Ver.4.04.01). : C/C++ compiler package for the SuperH RISC engine family : : None H/W Platform: M3A-HS64G50 (CPU board) Description : History : Mar.09,2009 Ver.1.00.00 (Ver.9.02 Release00). TO THE MAXIMUM EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS TECHNOLOGY CORP. NOR ANY OF ITS AFFILIATED COMPANIES SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THE THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. DISCLAIMED. ALL SUCH WARRANTIES ARE EXPRESSLY This software is owned by Renesas Technology Corp. and is protected under all applicable laws, including copyright laws. This software is supplied by Renesas Technology Corp. and is only intended for use with Renesas products. No other uses are authorized. DISCLAIMER
******************************************************************************** *""FILE COMMENT""*********** Technical reference data **************************
******************************************************************************** *""FILE COMMENT END""**********************************************************/
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Sample Program Listing "serial_flash.h" (2/2)
#ifndef _SERIAL_FLASH_H_ #define _SERIAL_FLASH_H_ /* ==== Macro definition ==== */ #define SF_PAGE_SIZE #define SF_SECTOR_SIZE #define SF_NUM_OF_SECTOR enum sf_req{ SF_REQ_PROTECT = 0, SF_REQ_UNPROTECT }; /* ==== Function prototype declaration ==== */ void sf_init_serial_flash(void); void sf_protect_ctrl(enum sf_req req); void sf_chip_erase(void); void sf_sector_erase(int sector_no); void sf_byte_program(unsigned long addr, unsigned char *buf, int size); void sf_byte_read(unsigned long addr, unsigned char *buf, int size); void sf_byte_read_long(unsigned long addr, unsigned long *buf, int size); /* ==== Variable definition ==== */ #endif /* _SERIAL_FLASH_H_ */ /* End of File */ /* Requests to protect */ /* Requests to unprotect */ 256 0x10000 32 /* Page size of serial flash memory */ /* Sector size = 64 KB /* Number of sectors: 32 */ */
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4.
References
* Software Manual SH-2A/SH-2A-FPU Software Manual Rev. 3.00 (Download the latest version from the Renesas website.) * Hardware Manual SH7262 Group, SH7264 Group Hardware Manual Rev. 1.00 (Download the latest version from the Renesas website.)
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Website and Support
Renesas Technology Website http://www.renesas.com/ Inquiries http://www.renesas.com/inquiry csc@renesas.com
Revision History
Rev. 1.00 Date Jun 30, 2009 Description Page Summary -- First edition issued
All trademarks and registered trademarks are the property of their respective owners.
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Notes regarding these materials
1. This document is provided for reference purposes only so that Renesas customers may select the appropriate Renesas products for their use. Renesas neither makes warranties or representations with respect to the accuracy or completeness of the information contained in this document nor grants any license to any intellectual property rights or any other rights of Renesas or any third party with respect to the information in this document. 2. Renesas shall have no liability for damages or infringement of any intellectual property or other rights arising out of the use of any information in this document, including, but not limited to, product data, diagrams, charts, programs, algorithms, and application circuit examples. 3. You should not use the products or the technology described in this document for the purpose of military applications such as the development of weapons of mass destruction or for the purpose of any other military use. When exporting the products or technology described herein, you should follow the applicable export control laws and regulations, and procedures required by such laws and regulations. 4. All information included in this document such as product data, diagrams, charts, programs, algorithms, and application circuit examples, is current as of the date this document is issued. Such information, however, is subject to change without any prior notice. Before purchasing or using any Renesas products listed in this document, please confirm the latest product information with a Renesas sales office. Also, please pay regular and careful attention to additional and different information to be disclosed by Renesas such as that disclosed through our website. (http://www.renesas.com ) 5. Renesas has used reasonable care in compiling the information included in this document, but Renesas assumes no liability whatsoever for any damages incurred as a result of errors or omissions in the information included in this document. 6. When using or otherwise relying on the information in this document, you should evaluate the information in light of the total system before deciding about the applicability of such information to the intended application. Renesas makes no representations, warranties or guaranties regarding the suitability of its products for any particular application and specifically disclaims any liability arising out of the application and use of the information in this document or Renesas products. 7. With the exception of products specified by Renesas as suitable for automobile applications, Renesas products are not designed, manufactured or tested for applications or otherwise in systems the failure or malfunction of which may cause a direct threat to human life or create a risk of human injury or which require especially high quality and reliability such as safety systems, or equipment or systems for transportation and traffic, healthcare, combustion control, aerospace and aeronautics, nuclear power, or undersea communication transmission. If you are considering the use of our products for such purposes, please contact a Renesas sales office beforehand. Renesas shall have no liability for damages arising out of the uses set forth above. 8. Notwithstanding the preceding paragraph, you should not use Renesas products for the purposes listed below: (1) artificial life support devices or systems (2) surgical implantations (3) healthcare intervention (e.g., excision, administration of medication, etc.) (4) any other purposes that pose a direct threat to human life Renesas shall have no liability for damages arising out of the uses set forth in the above and purchasers who elect to use Renesas products in any of the foregoing applications shall indemnify and hold harmless Renesas Technology Corp., its affiliated companies and their officers, directors, and employees against any and all damages arising out of such applications. 9. You should use the products described herein within the range specified by Renesas, especially with respect to the maximum rating, operating supply voltage range, movement power voltage range, heat radiation characteristics, installation and other product characteristics. Renesas shall have no liability for malfunctions or damages arising out of the use of Renesas products beyond such specified ranges. 10. Although Renesas endeavors to improve the quality and reliability of its products, IC products have specific characteristics such as the occurrence of failure at a certain rate and malfunctions under certain use conditions. Please be sure to implement safety measures to guard against the possibility of physical injury, and injury or damage caused by fire in the event of the failure of a Renesas product, such as safety design for hardware and software including but not limited to redundancy, fire control and malfunction prevention, appropriate treatment for aging degradation or any other applicable measures. Among others, since the evaluation of microcomputer software alone is very difficult, please evaluate the safety of the final products or system manufactured by you. 11. In case Renesas products listed in this document are detached from the products to which the Renesas products are attached or affixed, the risk of accident such as swallowing by infants and small children is very high. You should implement safety measures so that Renesas products may not be easily detached from your products. Renesas shall have no liability for damages arising out of such detachment. 12. This document may not be reproduced or duplicated, in any form, in whole or in part, without prior written approval from Renesas. 13. Please contact a Renesas sales office if you have any questions regarding the information contained in this document, Renesas semiconductor products, or if you have any other inquiries.

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